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<title>AArch64 Options (Using the GNU Compiler Collection (GCC))</title>

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Next: <a href="Adapteva-Epiphany-Options.html" accesskey="n" rel="next">Adapteva Epiphany Options</a>, Up: <a href="Submodel-Options.html" accesskey="u" rel="up">Machine-Dependent Options</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Indices.html" title="Index" rel="index">Index</a>]</p>
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<hr>
<h4 class="subsection" id="AArch64-Options-1"><span>3.19.1 AArch64 Options<a class="copiable-link" href="#AArch64-Options-1"> &para;</a></span></h4>
<a class="index-entry-id" id="index-AArch64-Options"></a>

<p>These options are defined for AArch64 implementations:
</p>
<dl class="table">
<dt><a id="index-mabi"></a><span><code class="code">-mabi=<var class="var">name</var></code><a class="copiable-link" href="#index-mabi"> &para;</a></span></dt>
<dd><p>Generate code for the specified data model.  Permissible values
are &lsquo;<samp class="samp">ilp32</samp>&rsquo; for SysV-like data model where int, long int and pointers
are 32 bits, and &lsquo;<samp class="samp">lp64</samp>&rsquo; for SysV-like data model where int is 32 bits,
but long int and pointers are 64 bits.
</p>
<p>The default depends on the specific target configuration.  Note that
the LP64 and ILP32 ABIs are not link-compatible; you must compile your
entire program with the same ABI, and link with a compatible set of libraries.
</p>
</dd>
<dt><a id="index-mbig_002dendian"></a><span><code class="code">-mbig-endian</code><a class="copiable-link" href="#index-mbig_002dendian"> &para;</a></span></dt>
<dd><p>Generate big-endian code.  This is the default when GCC is configured for an
&lsquo;<samp class="samp">aarch64_be-*-*</samp>&rsquo; target.
</p>
</dd>
<dt><a id="index-mgeneral_002dregs_002donly"></a><span><code class="code">-mgeneral-regs-only</code><a class="copiable-link" href="#index-mgeneral_002dregs_002donly"> &para;</a></span></dt>
<dd><p>Generate code which uses only the general-purpose registers.  This will prevent
the compiler from using floating-point and Advanced SIMD registers but will not
impose any restrictions on the assembler.
</p>
</dd>
<dt><a id="index-mlittle_002dendian"></a><span><code class="code">-mlittle-endian</code><a class="copiable-link" href="#index-mlittle_002dendian"> &para;</a></span></dt>
<dd><p>Generate little-endian code.  This is the default when GCC is configured for an
&lsquo;<samp class="samp">aarch64-*-*</samp>&rsquo; but not an &lsquo;<samp class="samp">aarch64_be-*-*</samp>&rsquo; target.
</p>
</dd>
<dt><a id="index-mcmodel_003dtiny"></a><span><code class="code">-mcmodel=tiny</code><a class="copiable-link" href="#index-mcmodel_003dtiny"> &para;</a></span></dt>
<dd><p>Generate code for the tiny code model.  The program and its statically defined
symbols must be within 1MB of each other.  Programs can be statically or
dynamically linked.
</p>
</dd>
<dt><a id="index-mcmodel_003dsmall"></a><span><code class="code">-mcmodel=small</code><a class="copiable-link" href="#index-mcmodel_003dsmall"> &para;</a></span></dt>
<dd><p>Generate code for the small code model.  The program and its statically defined
symbols must be within 4GB of each other.  Programs can be statically or
dynamically linked.  This is the default code model.
</p>
</dd>
<dt><a id="index-mcmodel_003dlarge"></a><span><code class="code">-mcmodel=large</code><a class="copiable-link" href="#index-mcmodel_003dlarge"> &para;</a></span></dt>
<dd><p>Generate code for the large code model.  This makes no assumptions about
addresses and sizes of sections.  Programs can be statically linked only.  The
<samp class="option">-mcmodel=large</samp> option is incompatible with <samp class="option">-mabi=ilp32</samp>,
<samp class="option">-fpic</samp> and <samp class="option">-fPIC</samp>.
</p>
</dd>
<dt><a class="index-entry-id" id="index-mno_002dstrict_002dalign"></a>
<a id="index-mstrict_002dalign"></a><span><code class="code">-mstrict-align</code><a class="copiable-link" href="#index-mstrict_002dalign"> &para;</a></span></dt>
<dt><code class="code">-mno-strict-align</code></dt>
<dd><p>Avoid or allow generating memory accesses that may not be aligned on a natural
object boundary as described in the architecture specification.
</p>
</dd>
<dt><a class="index-entry-id" id="index-mno_002domit_002dleaf_002dframe_002dpointer"></a>
<a id="index-momit_002dleaf_002dframe_002dpointer"></a><span><code class="code">-momit-leaf-frame-pointer</code><a class="copiable-link" href="#index-momit_002dleaf_002dframe_002dpointer"> &para;</a></span></dt>
<dt><code class="code">-mno-omit-leaf-frame-pointer</code></dt>
<dd><p>Omit or keep the frame pointer in leaf functions.  The former behavior is the
default.
</p>
</dd>
<dt><a class="index-entry-id" id="index-mstack_002dprotector_002dguard_002dreg"></a>
<a class="index-entry-id" id="index-mstack_002dprotector_002dguard_002doffset"></a>
<a id="index-mstack_002dprotector_002dguard"></a><span><code class="code">-mstack-protector-guard=<var class="var">guard</var></code><a class="copiable-link" href="#index-mstack_002dprotector_002dguard"> &para;</a></span></dt>
<dt><code class="code">-mstack-protector-guard-reg=<var class="var">reg</var></code></dt>
<dt><code class="code">-mstack-protector-guard-offset=<var class="var">offset</var></code></dt>
<dd><p>Generate stack protection code using canary at <var class="var">guard</var>.  Supported
locations are &lsquo;<samp class="samp">global</samp>&rsquo; for a global canary or &lsquo;<samp class="samp">sysreg</samp>&rsquo; for a
canary in an appropriate system register.
</p>
<p>With the latter choice the options
<samp class="option">-mstack-protector-guard-reg=<var class="var">reg</var></samp> and
<samp class="option">-mstack-protector-guard-offset=<var class="var">offset</var></samp> furthermore specify
which system register to use as base register for reading the canary,
and from what offset from that base register. There is no default
register or offset as this is entirely for use within the Linux
kernel.
</p>
</dd>
<dt><a id="index-mtls_002ddialect_003ddesc"></a><span><code class="code">-mtls-dialect=desc</code><a class="copiable-link" href="#index-mtls_002ddialect_003ddesc"> &para;</a></span></dt>
<dd><p>Use TLS descriptors as the thread-local storage mechanism for dynamic accesses
of TLS variables.  This is the default.
</p>
</dd>
<dt><a id="index-mtls_002ddialect_003dtraditional"></a><span><code class="code">-mtls-dialect=traditional</code><a class="copiable-link" href="#index-mtls_002ddialect_003dtraditional"> &para;</a></span></dt>
<dd><p>Use traditional TLS as the thread-local storage mechanism for dynamic accesses
of TLS variables.
</p>
</dd>
<dt><a id="index-mtls_002dsize"></a><span><code class="code">-mtls-size=<var class="var">size</var></code><a class="copiable-link" href="#index-mtls_002dsize"> &para;</a></span></dt>
<dd><p>Specify bit size of immediate TLS offsets.  Valid values are 12, 24, 32, 48.
This option requires binutils 2.26 or newer.
</p>
</dd>
<dt><a class="index-entry-id" id="index-mno_002dfix_002dcortex_002da53_002d835769"></a>
<a id="index-mfix_002dcortex_002da53_002d835769"></a><span><code class="code">-mfix-cortex-a53-835769</code><a class="copiable-link" href="#index-mfix_002dcortex_002da53_002d835769"> &para;</a></span></dt>
<dt><code class="code">-mno-fix-cortex-a53-835769</code></dt>
<dd><p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769.
This involves inserting a NOP instruction between memory instructions and
64-bit integer multiply-accumulate instructions.
</p>
</dd>
<dt><a class="index-entry-id" id="index-mno_002dfix_002dcortex_002da53_002d843419"></a>
<a id="index-mfix_002dcortex_002da53_002d843419"></a><span><code class="code">-mfix-cortex-a53-843419</code><a class="copiable-link" href="#index-mfix_002dcortex_002da53_002d843419"> &para;</a></span></dt>
<dt><code class="code">-mno-fix-cortex-a53-843419</code></dt>
<dd><p>Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419.
This erratum workaround is made at link time and this will only pass the
corresponding flag to the linker.
</p>
</dd>
<dt><a class="index-entry-id" id="index-mno_002dlow_002dprecision_002drecip_002dsqrt"></a>
<a id="index-mlow_002dprecision_002drecip_002dsqrt"></a><span><code class="code">-mlow-precision-recip-sqrt</code><a class="copiable-link" href="#index-mlow_002dprecision_002drecip_002dsqrt"> &para;</a></span></dt>
<dt><code class="code">-mno-low-precision-recip-sqrt</code></dt>
<dd><p>Enable or disable the reciprocal square root approximation.
This option only has an effect if <samp class="option">-ffast-math</samp> or
<samp class="option">-funsafe-math-optimizations</samp> is used as well.  Enabling this reduces
precision of reciprocal square root results to about 16 bits for
single precision and to 32 bits for double precision.
</p>
</dd>
<dt><a class="index-entry-id" id="index-mno_002dlow_002dprecision_002dsqrt"></a>
<a id="index-mlow_002dprecision_002dsqrt"></a><span><code class="code">-mlow-precision-sqrt</code><a class="copiable-link" href="#index-mlow_002dprecision_002dsqrt"> &para;</a></span></dt>
<dt><code class="code">-mno-low-precision-sqrt</code></dt>
<dd><p>Enable or disable the square root approximation.
This option only has an effect if <samp class="option">-ffast-math</samp> or
<samp class="option">-funsafe-math-optimizations</samp> is used as well.  Enabling this reduces
precision of square root results to about 16 bits for
single precision and to 32 bits for double precision.
If enabled, it implies <samp class="option">-mlow-precision-recip-sqrt</samp>.
</p>
</dd>
<dt><a class="index-entry-id" id="index-mno_002dlow_002dprecision_002ddiv"></a>
<a id="index-mlow_002dprecision_002ddiv"></a><span><code class="code">-mlow-precision-div</code><a class="copiable-link" href="#index-mlow_002dprecision_002ddiv"> &para;</a></span></dt>
<dt><code class="code">-mno-low-precision-div</code></dt>
<dd><p>Enable or disable the division approximation.
This option only has an effect if <samp class="option">-ffast-math</samp> or
<samp class="option">-funsafe-math-optimizations</samp> is used as well.  Enabling this reduces
precision of division results to about 16 bits for
single precision and to 32 bits for double precision.
</p>
</dd>
<dt><code class="code">-mtrack-speculation</code></dt>
<dt><code class="code">-mno-track-speculation</code></dt>
<dd><p>Enable or disable generation of additional code to track speculative
execution through conditional branches.  The tracking state can then
be used by the compiler when expanding calls to
<code class="code">__builtin_speculation_safe_copy</code> to permit a more efficient code
sequence to be generated.
</p>
</dd>
<dt><code class="code">-moutline-atomics</code></dt>
<dt><code class="code">-mno-outline-atomics</code></dt>
<dd><p>Enable or disable calls to out-of-line helpers to implement atomic operations.
These helpers will, at runtime, determine if the LSE instructions from
ARMv8.1-A can be used; if not, they will use the load/store-exclusive
instructions that are present in the base ARMv8.0 ISA.
</p>
<p>This option is only applicable when compiling for the base ARMv8.0
instruction set.  If using a later revision, e.g. <samp class="option">-march=armv8.1-a</samp>
or <samp class="option">-march=armv8-a+lse</samp>, the ARMv8.1-Atomics instructions will be
used directly.  The same applies when using <samp class="option">-mcpu=</samp> when the
selected cpu supports the &lsquo;<samp class="samp">lse</samp>&rsquo; feature.
This option is on by default.
</p>
</dd>
<dt><a id="index-march"></a><span><code class="code">-march=<var class="var">name</var></code><a class="copiable-link" href="#index-march"> &para;</a></span></dt>
<dd><p>Specify the name of the target architecture and, optionally, one or
more feature modifiers.  This option has the form
<samp class="option">-march=<var class="var">arch</var><span class="r">{</span>+<span class="r">[</span>no<span class="r">]</span><var class="var">feature</var><span class="r">}*</span></samp>.
</p>
<p>The table below summarizes the permissible values for <var class="var">arch</var>
and the features that they enable by default:
</p>
<table class="multitable">
<thead><tr><th width="20%"><var class="var">arch</var> value</th><th width="20%">Architecture</th><th width="60%">Includes by default</th></tr></thead>
<tbody><tr><td width="20%">&lsquo;<samp class="samp">armv8-a</samp>&rsquo;</td><td width="20%">Armv8-A</td><td width="60%">&lsquo;<samp class="samp">+fp</samp>&rsquo;, &lsquo;<samp class="samp">+simd</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv8.1-a</samp>&rsquo;</td><td width="20%">Armv8.1-A</td><td width="60%">&lsquo;<samp class="samp">armv8-a</samp>&rsquo;, &lsquo;<samp class="samp">+crc</samp>&rsquo;, &lsquo;<samp class="samp">+lse</samp>&rsquo;, &lsquo;<samp class="samp">+rdma</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv8.2-a</samp>&rsquo;</td><td width="20%">Armv8.2-A</td><td width="60%">&lsquo;<samp class="samp">armv8.1-a</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv8.3-a</samp>&rsquo;</td><td width="20%">Armv8.3-A</td><td width="60%">&lsquo;<samp class="samp">armv8.2-a</samp>&rsquo;, &lsquo;<samp class="samp">+pauth</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv8.4-a</samp>&rsquo;</td><td width="20%">Armv8.4-A</td><td width="60%">&lsquo;<samp class="samp">armv8.3-a</samp>&rsquo;, &lsquo;<samp class="samp">+flagm</samp>&rsquo;, &lsquo;<samp class="samp">+fp16fml</samp>&rsquo;, &lsquo;<samp class="samp">+dotprod</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv8.5-a</samp>&rsquo;</td><td width="20%">Armv8.5-A</td><td width="60%">&lsquo;<samp class="samp">armv8.4-a</samp>&rsquo;, &lsquo;<samp class="samp">+sb</samp>&rsquo;, &lsquo;<samp class="samp">+ssbs</samp>&rsquo;, &lsquo;<samp class="samp">+predres</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv8.6-a</samp>&rsquo;</td><td width="20%">Armv8.6-A</td><td width="60%">&lsquo;<samp class="samp">armv8.5-a</samp>&rsquo;, &lsquo;<samp class="samp">+bf16</samp>&rsquo;, &lsquo;<samp class="samp">+i8mm</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv8.7-a</samp>&rsquo;</td><td width="20%">Armv8.7-A</td><td width="60%">&lsquo;<samp class="samp">armv8.6-a</samp>&rsquo;, &lsquo;<samp class="samp">+ls64</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv8.8-a</samp>&rsquo;</td><td width="20%">Armv8.8-a</td><td width="60%">&lsquo;<samp class="samp">armv8.7-a</samp>&rsquo;, &lsquo;<samp class="samp">+mops</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv9-a</samp>&rsquo;</td><td width="20%">Armv9-A</td><td width="60%">&lsquo;<samp class="samp">armv8.5-a</samp>&rsquo;, &lsquo;<samp class="samp">+sve</samp>&rsquo;, &lsquo;<samp class="samp">+sve2</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv9.1-a</samp>&rsquo;</td><td width="20%">Armv9.1-A</td><td width="60%">&lsquo;<samp class="samp">armv9-a</samp>&rsquo;, &lsquo;<samp class="samp">+bf16</samp>&rsquo;, &lsquo;<samp class="samp">+i8mm</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv9.2-a</samp>&rsquo;</td><td width="20%">Armv9.2-A</td><td width="60%">&lsquo;<samp class="samp">armv9.1-a</samp>&rsquo;, &lsquo;<samp class="samp">+ls64</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv9.3-a</samp>&rsquo;</td><td width="20%">Armv9.3-A</td><td width="60%">&lsquo;<samp class="samp">armv9.2-a</samp>&rsquo;, &lsquo;<samp class="samp">+mops</samp>&rsquo;</td></tr>
<tr><td width="20%">&lsquo;<samp class="samp">armv8-r</samp>&rsquo;</td><td width="20%">Armv8-R</td><td width="60%">&lsquo;<samp class="samp">armv8-r</samp>&rsquo;</td></tr>
</tbody>
</table>

<p>The value &lsquo;<samp class="samp">native</samp>&rsquo; is available on native AArch64 GNU/Linux and
causes the compiler to pick the architecture of the host system.  This
option has no effect if the compiler is unable to recognize the
architecture of the host system,
</p>
<p>The permissible values for <var class="var">feature</var> are listed in the sub-section
on <a class="ref" href="#aarch64_002dfeature_002dmodifiers"><samp class="option">-march</samp> and <samp class="option">-mcpu</samp>
Feature Modifiers</a>.  Where conflicting feature modifiers are
specified, the right-most feature is used.
</p>
<p>GCC uses <var class="var">name</var> to determine what kind of instructions it can emit
when generating assembly code.  If <samp class="option">-march</samp> is specified
without either of <samp class="option">-mtune</samp> or <samp class="option">-mcpu</samp> also being
specified, the code is tuned to perform well across a range of target
processors implementing the target architecture.
</p>
</dd>
<dt><a id="index-mtune"></a><span><code class="code">-mtune=<var class="var">name</var></code><a class="copiable-link" href="#index-mtune"> &para;</a></span></dt>
<dd><p>Specify the name of the target processor for which GCC should tune the
performance of the code.  Permissible values for this option are:
&lsquo;<samp class="samp">generic</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a35</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a53</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a55</samp>&rsquo;,
&lsquo;<samp class="samp">cortex-a57</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a72</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a73</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a75</samp>&rsquo;,
&lsquo;<samp class="samp">cortex-a76</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a76ae</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a77</samp>&rsquo;,
&lsquo;<samp class="samp">cortex-a65</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a65ae</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a34</samp>&rsquo;,
&lsquo;<samp class="samp">cortex-a78</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a78ae</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a78c</samp>&rsquo;,
&lsquo;<samp class="samp">ares</samp>&rsquo;, &lsquo;<samp class="samp">exynos-m1</samp>&rsquo;, &lsquo;<samp class="samp">emag</samp>&rsquo;, &lsquo;<samp class="samp">falkor</samp>&rsquo;,
&lsquo;<samp class="samp">neoverse-512tvb</samp>&rsquo;, &lsquo;<samp class="samp">neoverse-e1</samp>&rsquo;, &lsquo;<samp class="samp">neoverse-n1</samp>&rsquo;,
&lsquo;<samp class="samp">neoverse-n2</samp>&rsquo;, &lsquo;<samp class="samp">neoverse-v1</samp>&rsquo;, &lsquo;<samp class="samp">neoverse-v2</samp>&rsquo;, &lsquo;<samp class="samp">grace</samp>&rsquo;,
&lsquo;<samp class="samp">qdf24xx</samp>&rsquo;, &lsquo;<samp class="samp">saphira</samp>&rsquo;, &lsquo;<samp class="samp">phecda</samp>&rsquo;, &lsquo;<samp class="samp">xgene1</samp>&rsquo;, &lsquo;<samp class="samp">vulcan</samp>&rsquo;,
&lsquo;<samp class="samp">octeontx</samp>&rsquo;, &lsquo;<samp class="samp">octeontx81</samp>&rsquo;,  &lsquo;<samp class="samp">octeontx83</samp>&rsquo;,
&lsquo;<samp class="samp">octeontx2</samp>&rsquo;, &lsquo;<samp class="samp">octeontx2t98</samp>&rsquo;, &lsquo;<samp class="samp">octeontx2t96</samp>&rsquo;
&lsquo;<samp class="samp">octeontx2t93</samp>&rsquo;, &lsquo;<samp class="samp">octeontx2f95</samp>&rsquo;, &lsquo;<samp class="samp">octeontx2f95n</samp>&rsquo;,
&lsquo;<samp class="samp">octeontx2f95mm</samp>&rsquo;,
&lsquo;<samp class="samp">a64fx</samp>&rsquo;,
&lsquo;<samp class="samp">thunderx</samp>&rsquo;, &lsquo;<samp class="samp">thunderxt88</samp>&rsquo;,
&lsquo;<samp class="samp">thunderxt88p1</samp>&rsquo;, &lsquo;<samp class="samp">thunderxt81</samp>&rsquo;, &lsquo;<samp class="samp">tsv110</samp>&rsquo;,
&lsquo;<samp class="samp">thunderxt83</samp>&rsquo;, &lsquo;<samp class="samp">thunderx2t99</samp>&rsquo;, &lsquo;<samp class="samp">thunderx3t110</samp>&rsquo;, &lsquo;<samp class="samp">zeus</samp>&rsquo;,
&lsquo;<samp class="samp">cortex-a57.cortex-a53</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a72.cortex-a53</samp>&rsquo;,
&lsquo;<samp class="samp">cortex-a73.cortex-a35</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a73.cortex-a53</samp>&rsquo;,
&lsquo;<samp class="samp">cortex-a75.cortex-a55</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a76.cortex-a55</samp>&rsquo;,
&lsquo;<samp class="samp">cortex-r82</samp>&rsquo;, &lsquo;<samp class="samp">cortex-x1</samp>&rsquo;, &lsquo;<samp class="samp">cortex-x1c</samp>&rsquo;, &lsquo;<samp class="samp">cortex-x2</samp>&rsquo;,
&lsquo;<samp class="samp">cortex-x3</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a510</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a710</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a715</samp>&rsquo;,
&lsquo;<samp class="samp">ampere1</samp>&rsquo;, &lsquo;<samp class="samp">ampere1a</samp>&rsquo;, &lsquo;<samp class="samp">cobalt-100</samp>&rsquo; and &lsquo;<samp class="samp">native</samp>&rsquo;.
</p>
<p>The values &lsquo;<samp class="samp">cortex-a57.cortex-a53</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a72.cortex-a53</samp>&rsquo;,
&lsquo;<samp class="samp">cortex-a73.cortex-a35</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a73.cortex-a53</samp>&rsquo;,
&lsquo;<samp class="samp">cortex-a75.cortex-a55</samp>&rsquo;, &lsquo;<samp class="samp">cortex-a76.cortex-a55</samp>&rsquo; specify that GCC
should tune for a big.LITTLE system.
</p>
<p>The value &lsquo;<samp class="samp">neoverse-512tvb</samp>&rsquo; specifies that GCC should tune
for Neoverse cores that (a) implement SVE and (b) have a total vector
bandwidth of 512 bits per cycle.  In other words, the option tells GCC to
tune for Neoverse cores that can execute 4 128-bit Advanced SIMD arithmetic
instructions a cycle and that can execute an equivalent number of SVE
arithmetic instructions per cycle (2 for 256-bit SVE, 4 for 128-bit SVE).
This is more general than tuning for a specific core like Neoverse V1
but is more specific than the default tuning described below.
</p>
<p>Additionally on native AArch64 GNU/Linux systems the value
&lsquo;<samp class="samp">native</samp>&rsquo; tunes performance to the host system.  This option has no effect
if the compiler is unable to recognize the processor of the host system.
</p>
<p>Where none of <samp class="option">-mtune=</samp>, <samp class="option">-mcpu=</samp> or <samp class="option">-march=</samp>
are specified, the code is tuned to perform well across a range
of target processors.
</p>
<p>This option cannot be suffixed by feature modifiers.
</p>
</dd>
<dt><a id="index-mcpu"></a><span><code class="code">-mcpu=<var class="var">name</var></code><a class="copiable-link" href="#index-mcpu"> &para;</a></span></dt>
<dd><p>Specify the name of the target processor, optionally suffixed by one
or more feature modifiers.  This option has the form
<samp class="option">-mcpu=<var class="var">cpu</var><span class="r">{</span>+<span class="r">[</span>no<span class="r">]</span><var class="var">feature</var><span class="r">}*</span></samp>, where
the permissible values for <var class="var">cpu</var> are the same as those available
for <samp class="option">-mtune</samp>.  The permissible values for <var class="var">feature</var> are
documented in the sub-section on
<a class="ref" href="#aarch64_002dfeature_002dmodifiers"><samp class="option">-march</samp> and <samp class="option">-mcpu</samp>
Feature Modifiers</a>.  Where conflicting feature modifiers are
specified, the right-most feature is used.
</p>
<p>GCC uses <var class="var">name</var> to determine what kind of instructions it can emit when
generating assembly code (as if by <samp class="option">-march</samp>) and to determine
the target processor for which to tune for performance (as if
by <samp class="option">-mtune</samp>).  Where this option is used in conjunction
with <samp class="option">-march</samp> or <samp class="option">-mtune</samp>, those options take precedence
over the appropriate part of this option.
</p>
<p><samp class="option">-mcpu=neoverse-512tvb</samp> is special in that it does not refer
to a specific core, but instead refers to all Neoverse cores that
(a) implement SVE and (b) have a total vector bandwidth of 512 bits
a cycle.  Unless overridden by <samp class="option">-march</samp>,
<samp class="option">-mcpu=neoverse-512tvb</samp> generates code that can run on a
Neoverse V1 core, since Neoverse V1 is the first Neoverse core with
these properties.  Unless overridden by <samp class="option">-mtune</samp>,
<samp class="option">-mcpu=neoverse-512tvb</samp> tunes code in the same way as for
<samp class="option">-mtune=neoverse-512tvb</samp>.
</p>
</dd>
<dt><a id="index-moverride"></a><span><code class="code">-moverride=<var class="var">string</var></code><a class="copiable-link" href="#index-moverride"> &para;</a></span></dt>
<dd><p>Override tuning decisions made by the back-end in response to a
<samp class="option">-mtune=</samp> switch.  The syntax, semantics, and accepted values
for <var class="var">string</var> in this option are not guaranteed to be consistent
across releases.
</p>
<p>This option is only intended to be useful when developing GCC.
</p>
</dd>
<dt><a id="index-mverbose_002dcost_002ddump"></a><span><code class="code">-mverbose-cost-dump</code><a class="copiable-link" href="#index-mverbose_002dcost_002ddump"> &para;</a></span></dt>
<dd><p>Enable verbose cost model dumping in the debug dump files.  This option is
provided for use in debugging the compiler.
</p>
</dd>
<dt><a class="index-entry-id" id="index-mno_002dpc_002drelative_002dliteral_002dloads"></a>
<a id="index-mpc_002drelative_002dliteral_002dloads"></a><span><code class="code">-mpc-relative-literal-loads</code><a class="copiable-link" href="#index-mpc_002drelative_002dliteral_002dloads"> &para;</a></span></dt>
<dt><code class="code">-mno-pc-relative-literal-loads</code></dt>
<dd><p>Enable or disable PC-relative literal loads.  With this option literal pools are
accessed using a single instruction and emitted after each function.  This
limits the maximum size of functions to 1MB.  This is enabled by default for
<samp class="option">-mcmodel=tiny</samp>.
</p>
</dd>
<dt><a id="index-msign_002dreturn_002daddress"></a><span><code class="code">-msign-return-address=<var class="var">scope</var></code><a class="copiable-link" href="#index-msign_002dreturn_002daddress"> &para;</a></span></dt>
<dd><p>Select the function scope on which return address signing will be applied.
Permissible values are &lsquo;<samp class="samp">none</samp>&rsquo;, which disables return address signing,
&lsquo;<samp class="samp">non-leaf</samp>&rsquo;, which enables pointer signing for functions which are not leaf
functions, and &lsquo;<samp class="samp">all</samp>&rsquo;, which enables pointer signing for all functions.  The
default value is &lsquo;<samp class="samp">none</samp>&rsquo;. This option has been deprecated by
-mbranch-protection.
</p>
</dd>
<dt><a id="index-mbranch_002dprotection"></a><span><code class="code">-mbranch-protection=<var class="var">none</var>|<var class="var">standard</var>|<var class="var">pac-ret</var>[+<var class="var">leaf</var>+<var class="var">b-key</var>]|<var class="var">bti</var></code><a class="copiable-link" href="#index-mbranch_002dprotection"> &para;</a></span></dt>
<dd><p>Select the branch protection features to use.
&lsquo;<samp class="samp">none</samp>&rsquo; is the default and turns off all types of branch protection.
&lsquo;<samp class="samp">standard</samp>&rsquo; turns on all types of branch protection features.  If a feature
has additional tuning options, then &lsquo;<samp class="samp">standard</samp>&rsquo; sets it to its standard
level.
&lsquo;<samp class="samp">pac-ret[+<var class="var">leaf</var>]</samp>&rsquo; turns on return address signing to its standard
level: signing functions that save the return address to memory (non-leaf
functions will practically always do this) using the a-key.  The optional
argument &lsquo;<samp class="samp">leaf</samp>&rsquo; can be used to extend the signing to include leaf
functions.  The optional argument &lsquo;<samp class="samp">b-key</samp>&rsquo; can be used to sign the functions
with the B-key instead of the A-key.
&lsquo;<samp class="samp">bti</samp>&rsquo; turns on branch target identification mechanism.
</p>
</dd>
<dt><a id="index-mharden_002dsls"></a><span><code class="code">-mharden-sls=<var class="var">opts</var></code><a class="copiable-link" href="#index-mharden_002dsls"> &para;</a></span></dt>
<dd><p>Enable compiler hardening against straight line speculation (SLS).
<var class="var">opts</var> is a comma-separated list of the following options:
</p><dl class="table">
<dt>&lsquo;<samp class="samp">retbr</samp>&rsquo;</dt>
<dt>&lsquo;<samp class="samp">blr</samp>&rsquo;</dt>
</dl>
<p>In addition, &lsquo;<samp class="samp">-mharden-sls=all</samp>&rsquo; enables all SLS hardening while
&lsquo;<samp class="samp">-mharden-sls=none</samp>&rsquo; disables all SLS hardening.
</p>
</dd>
<dt><a id="index-msve_002dvector_002dbits"></a><span><code class="code">-msve-vector-bits=<var class="var">bits</var></code><a class="copiable-link" href="#index-msve_002dvector_002dbits"> &para;</a></span></dt>
<dd><p>Specify the number of bits in an SVE vector register.  This option only has
an effect when SVE is enabled.
</p>
<p>GCC supports two forms of SVE code generation: &ldquo;vector-length
agnostic&rdquo; output that works with any size of vector register and
&ldquo;vector-length specific&rdquo; output that allows GCC to make assumptions
about the vector length when it is useful for optimization reasons.
The possible values of &lsquo;<samp class="samp">bits</samp>&rsquo; are: &lsquo;<samp class="samp">scalable</samp>&rsquo;, &lsquo;<samp class="samp">128</samp>&rsquo;,
&lsquo;<samp class="samp">256</samp>&rsquo;, &lsquo;<samp class="samp">512</samp>&rsquo;, &lsquo;<samp class="samp">1024</samp>&rsquo; and &lsquo;<samp class="samp">2048</samp>&rsquo;.
Specifying &lsquo;<samp class="samp">scalable</samp>&rsquo; selects vector-length agnostic
output.  At present &lsquo;<samp class="samp">-msve-vector-bits=128</samp>&rsquo; also generates vector-length
agnostic output for big-endian targets.  All other values generate
vector-length specific code.  The behavior of these values may change
in future releases and no value except &lsquo;<samp class="samp">scalable</samp>&rsquo; should be
relied on for producing code that is portable across different
hardware SVE vector lengths.
</p>
<p>The default is &lsquo;<samp class="samp">-msve-vector-bits=scalable</samp>&rsquo;, which produces
vector-length agnostic code.
</p></dd>
</dl>

<ul class="mini-toc">
<li><a href="#g_t_002dmarch-and-_002dmcpu-Feature-Modifiers" accesskey="1"><samp class="option">-march</samp> and <samp class="option">-mcpu</samp> Feature Modifiers</a></li>
</ul>
<div class="subsubsection-level-extent" id="g_t_002dmarch-and-_002dmcpu-Feature-Modifiers">
<h4 class="subsubsection"><span>3.19.1.1 <samp class="option">-march</samp> and <samp class="option">-mcpu</samp> Feature Modifiers<a class="copiable-link" href="#g_t_002dmarch-and-_002dmcpu-Feature-Modifiers"> &para;</a></span></h4>
<a class="anchor" id="aarch64_002dfeature_002dmodifiers"></a><a class="index-entry-id" id="index-_002dmarch-feature-modifiers"></a>
<a class="index-entry-id" id="index-_002dmcpu-feature-modifiers"></a>
<p>Feature modifiers used with <samp class="option">-march</samp> and <samp class="option">-mcpu</samp> can be any of
the following and their inverses <samp class="option">no<var class="var">feature</var></samp>:
</p>
<dl class="table">
<dt>&lsquo;<samp class="samp">crc</samp>&rsquo;</dt>
<dd><p>Enable CRC extension.  This is on by default for
<samp class="option">-march=armv8.1-a</samp>.
</p></dd>
<dt>&lsquo;<samp class="samp">crypto</samp>&rsquo;</dt>
<dd><p>Enable Crypto extension.  This also enables Advanced SIMD and floating-point
instructions.
</p></dd>
<dt>&lsquo;<samp class="samp">fp</samp>&rsquo;</dt>
<dd><p>Enable floating-point instructions.  This is on by default for all possible
values for options <samp class="option">-march</samp> and <samp class="option">-mcpu</samp>.
</p></dd>
<dt>&lsquo;<samp class="samp">simd</samp>&rsquo;</dt>
<dd><p>Enable Advanced SIMD instructions.  This also enables floating-point
instructions.  This is on by default for all possible values for options
<samp class="option">-march</samp> and <samp class="option">-mcpu</samp>.
</p></dd>
<dt>&lsquo;<samp class="samp">sve</samp>&rsquo;</dt>
<dd><p>Enable Scalable Vector Extension instructions.  This also enables Advanced
SIMD and floating-point instructions.
</p></dd>
<dt>&lsquo;<samp class="samp">lse</samp>&rsquo;</dt>
<dd><p>Enable Large System Extension instructions.  This is on by default for
<samp class="option">-march=armv8.1-a</samp>.
</p></dd>
<dt>&lsquo;<samp class="samp">rdma</samp>&rsquo;</dt>
<dd><p>Enable Round Double Multiply Accumulate instructions.  This is on by default
for <samp class="option">-march=armv8.1-a</samp>.
</p></dd>
<dt>&lsquo;<samp class="samp">fp16</samp>&rsquo;</dt>
<dd><p>Enable FP16 extension.  This also enables floating-point instructions.
</p></dd>
<dt>&lsquo;<samp class="samp">fp16fml</samp>&rsquo;</dt>
<dd><p>Enable FP16 fmla extension.  This also enables FP16 extensions and
floating-point instructions. This option is enabled by default for <samp class="option">-march=armv8.4-a</samp>. Use of this option with architectures prior to Armv8.2-A is not supported.
</p>
</dd>
<dt>&lsquo;<samp class="samp">rcpc</samp>&rsquo;</dt>
<dd><p>Enable the RCpc extension.  This enables the use of the LDAPR instructions for
load-acquire atomic semantics, and passes it on to the assembler, enabling
inline asm statements to use instructions from the RCpc extension.
</p></dd>
<dt>&lsquo;<samp class="samp">dotprod</samp>&rsquo;</dt>
<dd><p>Enable the Dot Product extension.  This also enables Advanced SIMD instructions.
</p></dd>
<dt>&lsquo;<samp class="samp">aes</samp>&rsquo;</dt>
<dd><p>Enable the Armv8-a aes and pmull crypto extension.  This also enables Advanced
SIMD instructions.
</p></dd>
<dt>&lsquo;<samp class="samp">sha2</samp>&rsquo;</dt>
<dd><p>Enable the Armv8-a sha2 crypto extension.  This also enables Advanced SIMD instructions.
</p></dd>
<dt>&lsquo;<samp class="samp">sha3</samp>&rsquo;</dt>
<dd><p>Enable the sha512 and sha3 crypto extension.  This also enables Advanced SIMD
instructions. Use of this option with architectures prior to Armv8.2-A is not supported.
</p></dd>
<dt>&lsquo;<samp class="samp">sm4</samp>&rsquo;</dt>
<dd><p>Enable the sm3 and sm4 crypto extension.  This also enables Advanced SIMD instructions.
Use of this option with architectures prior to Armv8.2-A is not supported.
</p></dd>
<dt>&lsquo;<samp class="samp">profile</samp>&rsquo;</dt>
<dd><p>Enable the Statistical Profiling extension.  This option is only to enable the
extension at the assembler level and does not affect code generation.
</p></dd>
<dt>&lsquo;<samp class="samp">rng</samp>&rsquo;</dt>
<dd><p>Enable the Armv8.5-a Random Number instructions.  This option is only to
enable the extension at the assembler level and does not affect code
generation.
</p></dd>
<dt>&lsquo;<samp class="samp">memtag</samp>&rsquo;</dt>
<dd><p>Enable the Armv8.5-a Memory Tagging Extensions.
Use of this option with architectures prior to Armv8.5-A is not supported.
</p></dd>
<dt>&lsquo;<samp class="samp">sb</samp>&rsquo;</dt>
<dd><p>Enable the Armv8-a Speculation Barrier instruction.  This option is only to
enable the extension at the assembler level and does not affect code
generation.  This option is enabled by default for <samp class="option">-march=armv8.5-a</samp>.
</p></dd>
<dt>&lsquo;<samp class="samp">ssbs</samp>&rsquo;</dt>
<dd><p>Enable the Armv8-a Speculative Store Bypass Safe instruction.  This option
is only to enable the extension at the assembler level and does not affect code
generation.  This option is enabled by default for <samp class="option">-march=armv8.5-a</samp>.
</p></dd>
<dt>&lsquo;<samp class="samp">predres</samp>&rsquo;</dt>
<dd><p>Enable the Armv8-a Execution and Data Prediction Restriction instructions.
This option is only to enable the extension at the assembler level and does
not affect code generation.  This option is enabled by default for
<samp class="option">-march=armv8.5-a</samp>.
</p></dd>
<dt>&lsquo;<samp class="samp">sve2</samp>&rsquo;</dt>
<dd><p>Enable the Armv8-a Scalable Vector Extension 2.  This also enables SVE
instructions.
</p></dd>
<dt>&lsquo;<samp class="samp">sve2-bitperm</samp>&rsquo;</dt>
<dd><p>Enable SVE2 bitperm instructions.  This also enables SVE2 instructions.
</p></dd>
<dt>&lsquo;<samp class="samp">sve2-sm4</samp>&rsquo;</dt>
<dd><p>Enable SVE2 sm4 instructions.  This also enables SVE2 instructions.
</p></dd>
<dt>&lsquo;<samp class="samp">sve2-aes</samp>&rsquo;</dt>
<dd><p>Enable SVE2 aes instructions.  This also enables SVE2 instructions.
</p></dd>
<dt>&lsquo;<samp class="samp">sve2-sha3</samp>&rsquo;</dt>
<dd><p>Enable SVE2 sha3 instructions.  This also enables SVE2 instructions.
</p></dd>
<dt>&lsquo;<samp class="samp">tme</samp>&rsquo;</dt>
<dd><p>Enable the Transactional Memory Extension.
</p></dd>
<dt>&lsquo;<samp class="samp">i8mm</samp>&rsquo;</dt>
<dd><p>Enable 8-bit Integer Matrix Multiply instructions.  This also enables
Advanced SIMD and floating-point instructions.  This option is enabled by
default for <samp class="option">-march=armv8.6-a</samp>.  Use of this option with architectures
prior to Armv8.2-A is not supported.
</p></dd>
<dt>&lsquo;<samp class="samp">f32mm</samp>&rsquo;</dt>
<dd><p>Enable 32-bit Floating point Matrix Multiply instructions.  This also enables
SVE instructions.  Use of this option with architectures prior to Armv8.2-A is
not supported.
</p></dd>
<dt>&lsquo;<samp class="samp">f64mm</samp>&rsquo;</dt>
<dd><p>Enable 64-bit Floating point Matrix Multiply instructions.  This also enables
SVE instructions.  Use of this option with architectures prior to Armv8.2-A is
not supported.
</p></dd>
<dt>&lsquo;<samp class="samp">bf16</samp>&rsquo;</dt>
<dd><p>Enable brain half-precision floating-point instructions.  This also enables
Advanced SIMD and floating-point instructions.  This option is enabled by
default for <samp class="option">-march=armv8.6-a</samp>.  Use of this option with architectures
prior to Armv8.2-A is not supported.
</p></dd>
<dt>&lsquo;<samp class="samp">ls64</samp>&rsquo;</dt>
<dd><p>Enable the 64-byte atomic load and store instructions for accelerators.
This option is enabled by default for <samp class="option">-march=armv8.7-a</samp>.
</p></dd>
<dt>&lsquo;<samp class="samp">mops</samp>&rsquo;</dt>
<dd><p>Enable the instructions to accelerate memory operations like <code class="code">memcpy</code>,
<code class="code">memmove</code>, <code class="code">memset</code>.  This option is enabled by default for
<samp class="option">-march=armv8.8-a</samp>
</p></dd>
<dt>&lsquo;<samp class="samp">flagm</samp>&rsquo;</dt>
<dd><p>Enable the Flag Manipulation instructions Extension.
</p></dd>
<dt>&lsquo;<samp class="samp">pauth</samp>&rsquo;</dt>
<dd><p>Enable the Pointer Authentication Extension.
</p></dd>
<dt>&lsquo;<samp class="samp">cssc</samp>&rsquo;</dt>
<dd><p>Enable the Common Short Sequence Compression instructions.
</p>
</dd>
</dl>

<p>Feature <samp class="option">crypto</samp> implies <samp class="option">aes</samp>, <samp class="option">sha2</samp>, and <samp class="option">simd</samp>,
which implies <samp class="option">fp</samp>.
Conversely, <samp class="option">nofp</samp> implies <samp class="option">nosimd</samp>, which implies
<samp class="option">nocrypto</samp>, <samp class="option">noaes</samp> and <samp class="option">nosha2</samp>.
</p>
</div>
</div>
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